This invention relates to integrated circuits such as programmable integrated circuits and more particularly, to emulating synchronous pipeline registers in integrated circuits with asynchronous interconnection elements.
Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced delays between synchronous elements, which has led to increased clock speeds and thus to an increase in the throughput of signals. However, recent technology nodes have seen a significant decrease in the incremental reduction of delays between synchronous elements and thus to smaller incremental increase in throughput. To further increase the throughput, solutions comprising the introduction of synchronous pipeline registers have been proposed. However, synchronous pipeline registers are susceptible to clock skew issues, which may limit the amount by which the speed of a clock may be increased.
An alternative is to use asynchronous interconnection elements. An asynchronous interconnection element conveys a signal from one asynchronous interconnection element to the next only when the next asynchronous interconnection element or the destination node is free to accept the signal. However, designing with asynchronous interconnection elements is difficult, and many design engineers are unfamiliar with asynchronous designs.